1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a circuit and a method of generating a boosted voltage for a semiconductor memory device including memory cell arrays.
A claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 2005-132860, filed on Dec. 29, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
There are a number of ways in which one may classify semiconductor memory devices. For example, semiconductor memory devices may be classified, according to a structure of memory cell arrays in the device. In this case, semiconductor memory devices may be classified into semiconductor memory devices having a folded bit line structure and semiconductor memory devices having an open bit line structure. Specifically, semiconductor memory devices may be classified into semiconductor memory devices having an 8F2 structure and semiconductor memory devices having a 6F2 structure based on an area that is occupied by a unit memory cell. To this end, in general, a semiconductor memory device having a folded bit line structure has the 8F2 structure and a semiconductor memory device having an open bit line structure has the 6F2 structure.
FIG. 1 is a circuit diagram illustrating a conventional memory cell array having an open bit line structure, which is disclosed in detail in U.S. patent application Ser. No. 6,535,439.
Referring to FIG. 1, the memory cell array 100 includes edge sub-arrays 120 and 140, non-edge sub-arrays 130, and sense amplifiers 151 through 159. Furthermore, the non-edge sub-arrays 130 include bit lines corresponding to horizontal lines and word lines corresponding to vertical lines. In addition, memory cells are located at the intersecting points of word lines and bit lines and at the intersecting points of word lines and dummy bit lines. In particular, the intersecting points are represented as dots in FIG. 1. As also shown in FIG. 1, a first bit line BL is coupled at one side of each of the sense amplifiers 154, 155, and 156 and a second bit line BLB is coupled at the other side of each of the sense amplifiers 154, 155, and 156. Furthermore, dummy bit lines DBL11, DB12, and DBL1n are coupled to one side of the sense amplifiers 151, 152 and 153, and a supply voltage VCC/2 is coupled to the other side of the sense amplifiers 151, 152 and 153. Similarly, dummy bit lines DBL21, DBL22, and DBL2n are coupled to one side of the sense amplifiers 157, 158, and 159, and a supply voltage VCC/2 is coupled to the other side of the sense amplifiers 157, 158, and 159.
FIG. 2 is a block diagram illustrating a conventional memory cell array including sub-arrays. Moreover, the sub-arrays include edge sub-arrays and non-edge sub-arrays. Furthermore, the non-edge sub-arrays are activated as shown in FIG. 2.
Referring to FIG. 2, the memory cell array 200 includes sub-arrays 210, 220, 230, 240, and 250. Furthermore, the memory cell array 200 is divided into two memory blocks BLOCK1 and BLOCK2. In addition, the sub-arrays 220 and 240 are non-edge sub-arrays, and the sub-arrays 210, 230 and 250 are edge sub-arrays. In FIG. 2, the non-edge sub-arrays 220 and 240 are activated at the same time in response to a word line enable signal WLE.
FIG. 3 is a block diagram illustrating a conventional memory cell array including edge sub-arrays that are activated in response to a common signal. Referring to FIG. 3, the memory cell array 300 includes sub-arrays 310, 320, 330, 340 and 350. Furthermore, the memory cell array 300 is divided into two memory blocks BLOCK1 and BLOCK2. In FIG. 3, the sub-arrays 320 and 340 are non-edge sub-arrays, and the sub-arrays 310, 330 and 350 are edge sub-arrays. Furthermore, the edge sub-arrays 310, 330, and 350 are activated at the same time in response to a word line enable signal WLE.
As seen above, in FIG. 2, two non-edge sub-arrays are activated at the same time, whereas in FIG. 3, three edge sub-arrays are activated at the same time. Thus, a number of non-edge sub-arrays that are activated at the same time may be different from a number of edge sub-arrays that are activated at the same time.
Accordingly, there may be a need for a boosted voltage generating circuit for generating a boosted voltage, where the circuit has different current driving capabilities for activating non-edge sub-arrays and edge sub-arrays.